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Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Solid-state electronics, 2013-03, Vol.81, p.101-104

2013

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Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Solid-state electronics, 2013-03, Vol.81, p.58-62

2013

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Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Microelectronic engineering, 2024-03, Vol.286, p.112130, Article 112130

2024

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Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Solid-state electronics, 2024-02, Vol.212, p.108835, Article 108835

2024

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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Interface traps density extraction through transient measurements in junctionless transistors

Solid-state electronics, 2022-08, Vol.194, p.108302, Article 108302

2022

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Microelectronic engineering, 2019-07, Vol.215, p.111005, Article 111005

2019

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Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Solid-state electronics, 2021-12, Vol.186, p.108097, Article 108097

2021

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Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Solid-state electronics, 2021-11, Vol.185, p.108072, Article 108072

2021

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Channel width dependent subthreshold operation of tri-gate junctionless transistors

Solid-state electronics, 2020-09, Vol.171, p.107860, Article 107860

2020

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Solid-state electronics, 2022-03, Vol.189, p.108223, Article 108223

2022

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Junctionless nanowire transistors parameters extraction based on drain current measurements

Solid-state electronics, 2019-08, Vol.158, p.37-45

2019

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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Impact of series resistance on the operation of junctionless transistors

Solid-state electronics, 2017-03, Vol.129, p.103-107

2017

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Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

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Back-gate effects and mobility characterization in junctionless transistor

Solid-state electronics, 2016-11, Vol.125, p.154-160

2016

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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

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Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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Series resistance in different operation regime of junctionless transistors

Solid-state electronics, 2018-03, Vol.141, p.92-95

2018

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Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Interface traps density extraction through transient measurements in junctionless transistors

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Junctionless nanowire transistors parameters extraction based on drain current measurements

Electrical characterization of stacked SOI nanowires at low temperatures

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Analog characteristics of n-type vertically stacked nanowires

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Impact of series resistance on the operation of junctionless transistors

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Back-gate effects and mobility characterization in junctionless transistor

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Electrical characterization of vertically stacked p-FET SOI nanowires

Series resistance in different operation regime of junctionless transistors

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