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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248-1252

2023

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{0,1}-Brauer Configuration Algebras and Their Applications in Graph Energy Theory

Mathematics (Basel), 2021-12, Vol.9 (23), p.3042

2021

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0/1 Knapsack Problem using Diversity based Dual Population Genetic Algorithm

International journal of intelligent systems and applications, 2014-09, Vol.6 (10), p.34-40

2014

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0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

Electronics (Basel), 2020-01, Vol.9 (1), p.133

2020

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A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

International journal of electronics, 2014-02, Vol.101 (2), p.182-193

2014

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A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

IEICE transactions on electronics, 2024-06, Vol.E107.C (6), p.155-162, Article 2023LHP0001

2024

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A 0.18- mu hbox m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

IEEE transactions on microwave theory and techniques, 2011-01, Vol.59 (1), p.116-124

2011

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0.18 µm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7±17.4 ps group-delay

Electronics letters, 2007-11, Vol.43 (24), p.1

2007

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0.18 µm 3-6 GHz CMOS broadband LNA for UWB radio

Electronics letters, 2005-06, Vol.41 (12), p.1

2005

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A 0.2-Terahertz Ceramic Relic Detection System Based on Iterative Threshold Filtering Imaging and Neural Network

Electronics (Basel), 2021-09, Vol.10 (18), p.2213

2021

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A 0.25-1.25-GHz High-Efficiency Power Amplifier With Computer-Aided Design Based on Optimized Impedance Solution Continuum

IEEE microwave and wireless components letters, 2018-05, Vol.28 (5), p.443-445

2018

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A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes

IEEE transactions on very large scale integration (VLSI) systems, 2022-09, Vol.30 (9), p.1281-1293

2022

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932

2020

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A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications

IEEE journal of biomedical and health informatics, 2015-05, Vol.19 (3), p.920-929

2015

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0.35 V time-domain-based instrumentation amplifier

Electronics letters, 2014-10, Vol.50 (21), p.1511-1513

2014

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A 0.35 μm sub-ns wake-up time ON-OFF switchable LVDS driver-receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links

IEEE transactions on biomedical circuits and systems, 2012-10, Vol.6 (5), p.486-497

2012

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A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface With Data Rate and Load Capacitance Adaptability

IEEE solid-state circuits letters, 2020, Vol.3, p.322-325

2020

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0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, + 10-dBm IB-IIP3 in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.1-13

2023

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A 0.4-2.3 GHz broadband power amplifier extended continuous class-F design technology

International journal of electronics, 2015-08, Vol.102 (8), p.1320-1333

2015

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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

IEEE journal of solid-state circuits, 2021-07, Vol.56 (7), p.2234-2244

2021

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A 0.45/0.2-NEF/PEF 12-nV/√Hz Highly Configurable Discrete-Time Low-Noise Amplifier

IEEE solid-state circuits letters, 2020, Vol.3, p.486-489

2020

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A 0.45 ppm and low phase noise analog crystal oscillator using a four order temperature compensation algorithm

International journal of electronics and communications, 2018-06, Vol.90, p.69-78

2018

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0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)

Journal of low power electronics and applications, 2018-06, Vol.8 (2), p.14

2018

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0.5-25 GHz inductorless single-ended resistive mixer in 0.13 µm CMOS

Electronics letters, 2009-01, Vol.45 (2), p.1

2009

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0.5 V inverter-based ultra-low-power, low-noise VGA for medical ultrasound probes

Electronics letters, 2014-01, Vol.50 (2), p.69-71

2014

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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

{0,1}-Brauer Configuration Algebras and Their Applications in Graph Energy Theory

0/1 Knapsack Problem using Diversity based Dual Population Genetic Algorithm

0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

A 0.18- mu hbox m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

0.18 µm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7±17.4 ps group-delay

0.18 µm 3-6 GHz CMOS broadband LNA for UWB radio

A 0.2-Terahertz Ceramic Relic Detection System Based on Iterative Threshold Filtering Imaging and Neural Network

A 0.25-1.25-GHz High-Efficiency Power Amplifier With Computer-Aided Design Based on Optimized Impedance Solution Continuum

A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications

0.35 V time-domain-based instrumentation amplifier

A 0.35 μm sub-ns wake-up time ON-OFF switchable LVDS driver-receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links

A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface With Data Rate and Load Capacitance Adaptability

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, + 10-dBm IB-IIP3 in 65-nm CMOS

A 0.4-2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

A 0.45/0.2-NEF/PEF 12-nV/√Hz Highly Configurable Discrete-Time Low-Noise Amplifier

A 0.45 ppm and low phase noise analog crystal oscillator using a four order temperature compensation algorithm

0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)

0.5-25 GHz inductorless single-ended resistive mixer in 0.13 µm CMOS

0.5 V inverter-based ultra-low-power, low-noise VGA for medical ultrasound probes

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