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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.423-432

2006

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IEEE_Xplore

Ten years of hardware Trojans: a survey from the attacker's perspective

IET computers & digital techniques, 2020-11, Vol.14 (6), p.231-246

2020

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Stochastic circuits for real-time image-processing applications

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-6

2013

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IEEE_Xplore

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.298-311

2018

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IEEE_Xplore

A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE MICRO, 2007-09, Vol.27 (5), p.51-61

2007

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IEEE_Xplore

Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management

IEEE transactions on information forensics and security, 2012-02, Vol.7 (1), p.51-63

Koushanfar, Farinaz

2012

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IEEE_Xplore

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

IEEE transactions on computers, 2014-06, Vol.63 (6), p.1336-1350

2014

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IEEE_Xplore

Future proof optical network infrastructure for 5G transport

Journal of optical communications and networking, 2016-12, Vol.8 (12), p.B80-B92

2016

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IEEE_Xplore

A New Outer Bound and the Noisy-Interference Sum-Rate Capacity for Gaussian Interference Channels

IEEE transactions on information theory, 2009-02, Vol.55 (2), p.689-699

2009

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IEEE_Xplore

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.25-37

2014

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IEEE_Xplore

Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-11, Vol.35 (11), p.1848-1861

2016

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IEEE_Xplore

Transparent Hardware Management of Stacked DRAM as Part of Memory

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.13-24

2014

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IEEE_Xplore

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008, p.222-233

2008

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IEEE_Xplore

3D-Stacked Memory Architectures for Multi-core Processors

2008 International Symposium on Computer Architecture, 2008, p.453-464

Loh, Gabriel

2008

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IEEE_Xplore

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

2008 International Symposium on Computer Architecture, 2008, p.229-240

2008

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IEEE_Xplore

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-03, Vol.41 (3), p.794-798

2022

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Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008, p.210-221

2008

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IEEE_Xplore

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

IET computers & digital techniques, 2021-09, Vol.15 (5), p.362-371

2021

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Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3137-3150

2018

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IEEE_Xplore

Ultrahigh Density Logic Designs Using Monolithic 3-D Integration

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-12, Vol.32 (12), p.1892-1905

2013

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IEEE_Xplore

Compact Topology-Aware Bus Routing for Design Regularity

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1744-1749

2020

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IEEE_Xplore

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.1396-1413

2022

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Optimal design of a CMOS op-amp via geometric programming

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-01, Vol.20 (1), p.1-21

2001

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IEEE_Xplore

High-power high-efficiency SiGe Ku- and Ka-band balanced frequency doublers

IEEE transactions on microwave theory and techniques, 2005-02, Vol.53 (2), p.754-761

2005

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IEEE_Xplore

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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Ten years of hardware Trojans: a survey from the attacker's perspective

Stochastic circuits for real-time image-processing applications

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

A 5-GHz Mesh Interconnect for a Teraflops Processor

Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

Future proof optical network infrastructure for 5G transport

A New Outer Bound and the Noisy-Interference Sum-Rate Capacity for Gaussian Interference Channels

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks

Transparent Hardware Management of Stacked DRAM as Part of Memory

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

3D-Stacked Memory Architectures for Multi-core Processors

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires

Ultrahigh Density Logic Designs Using Monolithic 3-D Integration

Compact Topology-Aware Bus Routing for Design Regularity

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture

Optimal design of a CMOS op-amp via geometric programming

High-power high-efficiency SiGe Ku- and Ka-band balanced frequency doublers

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