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FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

IEEE access, 2019, Vol.7, p.7823-7859

2019

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Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

IEEE Communications surveys and tutorials, 2019-01, Vol.21 (3), p.2309-2333

2019

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IEEE_Xplore

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.509-527

2010

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IEEE_Xplore

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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IEEE_Xplore

Synthesis and optimization of reversible circuits-a survey

ACM computing surveys, 2013-02, Vol.45 (2), p.1-34

2013

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A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-05, Vol.23 (5), p.678-693

2004

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IEEE_Xplore

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-01, Vol.28 (1), p.3-21

2009

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IEEE_Xplore

Functional Analysis Attacks on Logic Locking

IEEE transactions on information forensics and security, 2020, Vol.15, p.2514-2527

2020

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IEEE_Xplore

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

IEEE journal on exploratory solid-state computational devices and circuits, 2015-12, Vol.1, p.3-11

2015

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Recent thermal management techniques for microprocessors

ACM computing surveys, 2012-06, Vol.44 (3), p.1-42

2012

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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.423-432

2006

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IEEE_Xplore

VLSI Physical Design: From Graph Partitioning to Timing Closure

1, 2011

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Ten years of hardware Trojans: a survey from the attacker's perspective

IET computers & digital techniques, 2020-11, Vol.14 (6), p.231-246

2020

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Stochastic circuits for real-time image-processing applications

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-6

2013

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IEEE_Xplore

Provably Secure Camouflaging Strategy for IC Protection

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-08, Vol.38 (8), p.1399-1412

2019

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IEEE_Xplore

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.298-311

2018

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IEEE_Xplore

Hardware Optimized and Error Reduced Approximate Adder

Electronics (Basel), , Vol.8 (11), p.1212

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Design of Highly Linear Broadband Continuous Mode GaN MMIC Power Amplifiers for 5G

IEEE access, 2019, Vol.7, p.57138-57150

2019

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Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-06, Vol.39 (6), p.1231-1244

2020

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IEEE_Xplore

Capacity Bounds for the Gaussian Interference Channel

IEEE transactions on information theory, 2009-02, Vol.55 (2), p.620-643

2009

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IEEE_Xplore

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1591-1606

2020

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IEEE_Xplore

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

IEEE transactions on computers, 2009-01, Vol.58 (1), p.32-45

2009

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IEEE_Xplore

Mathematical Modeling Analysis of Strong Physical Unclonable Functions

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4426-4438

2020

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IEEE_Xplore

A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE MICRO, 2007-09, Vol.27 (5), p.51-61

2007

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IEEE_Xplore

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FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Synthesis and optimization of reversible circuits-a survey

A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

Functional Analysis Attacks on Logic Locking

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

Recent thermal management techniques for microprocessors

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

VLSI Physical Design: From Graph Partitioning to Timing Closure

Ten years of hardware Trojans: a survey from the attacker's perspective

Stochastic circuits for real-time image-processing applications

Provably Secure Camouflaging Strategy for IC Protection

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

Hardware Optimized and Error Reduced Approximate Adder

Design of Highly Linear Broadband Continuous Mode GaN MMIC Power Amplifiers for 5G

Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection

Capacity Bounds for the Gaussian Interference Channel

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

Mathematical Modeling Analysis of Strong Physical Unclonable Functions

A 5-GHz Mesh Interconnect for a Teraflops Processor

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