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Special size effects in advanced single-gate and multiple-gate SOI transistors

Journal of Telecommunications and Information Technology, 2023-06 (2), p.14-24

2023

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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.682-691

2024

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-03, Vol.31 (2)

2013

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Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Journal of applied physics, 2011-10, Vol.110 (8), p.084901-084901-9

2011

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Two-level Stacked Nanowire MOSFETs: A Low Temperature Analysis of the Low-Field Mobility Degradation Factors

Journal of Integrated Circuits and Systems, 2024-08, Vol.19 (2), p.1-5

2024

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Performance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion

Journal of Integrated Circuits and Systems, 2020-08, Vol.15 (2), p.1-5

2020

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High tolerance to total ionizing dose of Ω -shaped gate field-effect transistors

Applied physics letters, 2006-05, Vol.88 (22), p.223511-223511-3

2006

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Benefits and challenges of FDSOI technology for 14nm node

IEEE 2011 International SOI Conference, 2011, p.1-21

Faynot, O.

2011

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New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

2017 Symposium on VLSI Technology, 2017, p.T134-T135

2017

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Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.6E.6-1-6E.6-6

2018

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Analog performance of strained SOI nanowires down to 10K

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.222-225

2016

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(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

ECS transactions, 2016, Vol.75 (8), p.505-512

2016

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Opportunities brought by sequential 3D CoolCube™ integration

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.226-229

2016

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4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.355-358

2015

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On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process

ECS transactions, 2013, Vol.53 (3), p.177-184

2013

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Experimental Comparison of Junctionless and Inversion-Mode Nanowire SOI MOSFETs Down to Cryogenics Temperatures

2024 38th Symposium on Microelectronics Technology and Devices (SBMicro), 2024, p.1-4

2024

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Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011, p.75-78

2011

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Ultra-thin nanocrystalline diamond films (<100 nm) with high electrical resistivity

Physica status solidi. PSS-RRL. Rapid research letters, 2009-09, Vol.3 (6), p.205-207

2009

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Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length

2010 Proceedings of the European Solid State Device Research Conference, 2010, p.150-153

2010

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Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

2023 International Conference on Noise and Fluctuations (ICNF), 2023, p.1-4

2023

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Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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High Scalability and Low Variability of Planar Fully Depleted SOI MOSFETs

ECS transactions, 2009, Vol.22 (1), p.71-80

2009

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Special size effects in advanced single-gate and multiple-gate SOI transistors

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Two-level Stacked Nanowire MOSFETs: A Low Temperature Analysis of the Low-Field Mobility Degradation Factors

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Performance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion

High tolerance to total ionizing dose of Ω -shaped gate field-effect transistors

Benefits and challenges of FDSOI technology for 14nm node

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs

Analog performance of strained SOI nanowires down to 10K

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

Opportunities brought by sequential 3D CoolCube™ integration

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process

Experimental Comparison of Junctionless and Inversion-Mode Nanowire SOI MOSFETs Down to Cryogenics Temperatures

Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

Ultra-thin nanocrystalline diamond films (<100 nm) with high electrical resistivity

Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length

Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

High Scalability and Low Variability of Planar Fully Depleted SOI MOSFETs

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