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A 0.004mm/sup 2/ Portable Multiphase Clock Generator Tile for 1.2GHz RISC Microprocessor

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.104-105

2006

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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

2010 Symposium on VLSI Technology, 2010, p.19-20

2010

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A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

IEEE journal of solid-state circuits, 2007, Vol.42 (1), p.210-218

2007

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A 0.1-[mu]m 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.210-218

2007

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A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.101-102

2001

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0.15 μm gate length MHEMT technology for 77GHz automotive radar applications

2004

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A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

IEEE journal of solid-state circuits, 2005, Vol.40 (1), p.293-300

2005

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A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535), 2004, Vol.1, p.105-108 Vol.1

2004

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A 0.18/spl mu/m CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications

Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects, 2004, p.73-76

2004

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A 0.18/spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller for 4-PAM/20Gbps throughput transmission over backplane channels

Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects, 2004, p.179-182

2004

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A 0.18 /spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.4847-4850 Vol. 5

2005

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A 0.18 /spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), 2003, p.15-16

2003

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0.18 um modular triple self-aligned embedded split-gate flash memory

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, p.120-121

2000

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A 0.18um CMOS equalizer with a improved multiplier for 4-PAM/20Gbps throughput over 20-inch FR-4 backplane channels

2004

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A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

29th European Solid-State Device Research Conference, 1999, Vol.1, p.632-635

1999

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A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

First edition, 2004

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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

IEEE journal of solid-state circuits, 2008-02, Vol.43 (2), p.518-529

2008

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0.3-nm SASE-FEL at PAL

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2004-08, Vol.528 (1), p.582-585

2004

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0.37 mS/μm In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

2009 Device Research Conference, 2009, p.253-254

2009

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000149 HUMAN PAPILLOMAVIRUS GENOTYPING BY HPV DNA CHIP IN KOREAN WOMEN

International journal of gynecological cancer, 2005-09, Vol.15 (Suppl 2), p.93-93

2005

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000196 EIF-4E EXPRESSION IN THE PROGRESSION OF CERVICAL NEOPLASIA

International journal of gynecological cancer, 2005-09, Vol.15 (Suppl 2), p.106-106

2005

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000266 ALLELE LOSS AND PROMOTER HYPERMETHYLATION OF VHL, RAR-β, RASSF1A, AND FHIT TUMOR SUPPRESSOR GENES ON CHROMOSOME 3P IN CERVICAL SQUAMOUS CELL CARCINOMA

International journal of gynecological cancer, 2005-09, Vol.15 (Suppl 2), p.125-125

2005

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000268 PROTEOME ANALYSIS OF DIFFERENTIAL PROTEIN EXPRESSION IN CERVICAL CANCER CELLS AFTER PACLITAX-EL TREATMENT

International journal of gynecological cancer, 2005-09, Vol.15 (Suppl 2), p.126-126

2005

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000316 A STUDY ON THE NATURAL HISTORY OF THE ABNORMAL RESULTS OF PAP TEST IN CERVICAL CANCER SCREENING

International journal of gynecological cancer, 2005-09, Vol.15 (Suppl 2), p.138-138

2005

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1 – 25 von 54.029

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A 0.004mm/sup 2/ Portable Multiphase Clock Generator Tile for 1.2GHz RISC Microprocessor

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

A 0.1-[mu]m 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

0.15 μm gate length MHEMT technology for 77GHz automotive radar applications

A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

A 0.18/spl mu/m CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications

A 0.18/spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller for 4-PAM/20Gbps throughput transmission over backplane channels

A 0.18 /spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels

A 0.18 /spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications

0.18 um modular triple self-aligned embedded split-gate flash memory

A 0.18um CMOS equalizer with a improved multiplier for 4-PAM/20Gbps throughput over 20-inch FR-4 backplane channels

A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

0.3-nm SASE-FEL at PAL

0.37 mS/μm In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

000149 HUMAN PAPILLOMAVIRUS GENOTYPING BY HPV DNA CHIP IN KOREAN WOMEN

000196 EIF-4E EXPRESSION IN THE PROGRESSION OF CERVICAL NEOPLASIA

000266 ALLELE LOSS AND PROMOTER HYPERMETHYLATION OF VHL, RAR-β, RASSF1A, AND FHIT TUMOR SUPPRESSOR GENES ON CHROMOSOME 3P IN CERVICAL SQUAMOUS CELL CARCINOMA

000268 PROTEOME ANALYSIS OF DIFFERENTIAL PROTEIN EXPRESSION IN CERVICAL CANCER CELLS AFTER PACLITAX-EL TREATMENT

000316 A STUDY ON THE NATURAL HISTORY OF THE ABNORMAL RESULTS OF PAP TEST IN CERVICAL CANCER SCREENING

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