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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.638-651

2020

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New attacks and defense for encrypted-address cache

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.360-371

Qureshi, Moinuddin K.

2019

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IEEE_Xplore

Fault Analysis-Based Logic Encryption

IEEE transactions on computers, 2015-02, Vol.64 (2), p.410-424

2015

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IEEE_Xplore

Correct Hardware Design and Verification Methods: 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001 Livingston, Scotland, UK, September 4–7, 2001 Proceedings

2001

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Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

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An architecture-level analysis on deep learning models for low-impact computations

The Artificial intelligence review, 2023-03, Vol.56 (3), p.1971-2010

2023

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QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.944-957

2021

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IEEE_Xplore

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.132-144

2020

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Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1198-1213

2021

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OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1648-1661

2021

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Anti-SAT: Mitigating SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.199-207

2019

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IEEE_Xplore

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

IEEE access, 2019, Vol.7, p.7823-7859

2019

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A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1182-1197

2021

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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.255-268

2017

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TWiCe: preventing row-hammering by exploiting time window counters

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.385-396

2019

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IEEE_Xplore

CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.666-679

2020

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TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

Random Fill Cache Architecture

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.203-215

2014

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IEEE_Xplore

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1952-1956

2021

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IEEE_Xplore

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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IEEE_Xplore

Memristor Bridge Synapse-Based Neural Network and Its Learning

IEEE transaction on neural networks and learning systems, 2012-09, Vol.23 (9), p.1426-1435

2012

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IEEE_Xplore

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Correct Hardware Design and Verification Methods: 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003. Proceedings

2003

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Golden-Free Hardware Trojan Detection Using Self-Referencing

IEEE transactions on very large scale integration (VLSI) systems, 2022-03, Vol.30 (3), p.325-338

2022

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IEEE_Xplore

Recent advances in efficient computation of deep convolutional neural networks

Frontiers of information technology & electronic engineering, 2018, Vol.19 (1), p.64-77

2018

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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

New attacks and defense for encrypted-address cache

Fault Analysis-Based Logic Encryption

Correct Hardware Design and Verification Methods: 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001 Livingston, Scotland, UK, September 4–7, 2001 Proceedings

Hardware architecture and software stack for PIM based on commercial DRAM technology

An architecture-level analysis on deep learning models for low-impact computations

QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

Anti-SAT: Mitigating SAT Attack on Logic Locking

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

TWiCe: preventing row-hammering by exploiting time window counters

CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

Random Fill Cache Architecture

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Memristor Bridge Synapse-Based Neural Network and Its Learning

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Correct Hardware Design and Verification Methods: 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003. Proceedings

Golden-Free Hardware Trojan Detection Using Self-Referencing

Recent advances in efficient computation of deep convolutional neural networks

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