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Special size effects in advanced single-gate and multiple-gate SOI transistors

Journal of Telecommunications and Information Technology, 2023-06 (2), p.14-24

2023

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Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

IEEE transactions on nuclear science, 2013-08, Vol.60 (4), p.2583-2589

2013

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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.682-691

2024

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2326-2336

2011

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

IEEE electron device letters, 2012-03, Vol.33 (3), p.318-320

2012

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Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-03, Vol.31 (2)

2013

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Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Journal of applied physics, 2011-10, Vol.110 (8), p.084901-084901-9

2011

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Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2355-2362

2007

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Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011, Vol.58 (8), p.2473-2482

2011

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Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2473-2482

2011

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Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

2012 Symposium on VLSI Technology (VLSIT), 2012, p.113-114

2012

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Two-level Stacked Nanowire MOSFETs: A Low Temperature Analysis of the Low-Field Mobility Degradation Factors

Journal of Integrated Circuits and Systems, 2024-08, Vol.19 (2), p.1-5

2024

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Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

IEEE electron device letters, 2012-12, Vol.33 (12), p.1717-1719

2012

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BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

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GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

IEEE electron device letters, 2010-03, Vol.31 (3), p.234-236

2010

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Experimental Evaluation of 7-Level Stacked Nanosheet SOI MOSFETs Analog Parameters

2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, p.456-459

2024

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A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

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Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.1161-1167

2014

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A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1366-1375

2007

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Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

IEEE electron device letters, 2009-12, Vol.30 (12), p.1266-1268

2009

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Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.969-975

2014

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Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

IEEE electron device letters, 2013-07, Vol.34 (7), p.840-842

2013

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Special size effects in advanced single-gate and multiple-gate SOI transistors

Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Two-level Stacked Nanowire MOSFETs: A Low Temperature Analysis of the Low-Field Mobility Degradation Factors

Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Experimental Evaluation of 7-Level Stacked Nanosheet SOI MOSFETs Analog Parameters

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

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