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5.3 A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.92-94

2024

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IEEE_Xplore

3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy from -55°C to 125°C and a 200fJ·K2 Resolution FoM

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.66-68

2024

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IEEE_Xplore

14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.264-266

2024

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IEEE_Xplore

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.50-52

2024

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IEEE_Xplore

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.292-294

2024

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IEEE_Xplore

28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.462-464

2024

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IEEE_Xplore

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.578-580

2024

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IEEE_Xplore

14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.270-272

2024

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IEEE_Xplore

ISSCC 2024 Forum 5: Recent Developments in High-Performance Frequency Synthesis Circuits and Systems

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.605-608

2024

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IEEE_Xplore

ISSCC 2024 Forum 3: Digitally Enhanced Analog Circuits: Trends & State-of-the-art Designs

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.597-600

2024

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IEEE_Xplore

10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.202-204

2024

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IEEE_Xplore

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.130-132

2024

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IEEE_Xplore

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.236-237

2024

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IEEE_Xplore

ISSCC 2024 Panel Discussion

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.i-v

2024

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IEEE_Xplore

8.1 A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-Output Converter with a Concise PWM Control for AMOLED Displays

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.144-146

2024

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IEEE_Xplore

28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.464-466

2024

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IEEE_Xplore

33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.562-564

2024

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IEEE_Xplore

ISSCC 2024 Panel Discussion

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.i-vi

2024

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IEEE_Xplore

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.204-206

2024

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IEEE_Xplore

ISSCC 2024 Tutorials

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.585-588

2024

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IEEE_Xplore

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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IEEE_Xplore

3.2 A 0.028mm² 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from −40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.56-58

2024

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IEEE_Xplore

32.1 A 47GHz 4-way Doherty PA with 23.7dBm P1dB and 21.7% / 13.1% PAE at 6 / 12dB Back-off Supporting 2000MHz 5G NR 64-QAM OFDM

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.520-522

2024

Link zum Volltext
IEEE_Xplore

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.308-310

2024

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IEEE_Xplore

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.174-176

2024

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IEEE_Xplore

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5.3 A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS

3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy from -55°C to 125°C and a 200fJ·K2 Resolution FoM

14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes

28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing

14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS

ISSCC 2024 Forum 5: Recent Developments in High-Performance Frequency Synthesis Circuits and Systems

ISSCC 2024 Forum 3: Digitally Enhanced Analog Circuits: Trends & State-of-the-art Designs

10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

ISSCC 2024 Panel Discussion

8.1 A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-Output Converter with a Concise PWM Control for AMOLED Displays

28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM

33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition

ISSCC 2024 Panel Discussion

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment

ISSCC 2024 Tutorials

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

3.2 A 0.028mm² 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from −40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging

32.1 A 47GHz 4-way Doherty PA with 23.7dBm P1dB and 21.7% / 13.1% PAE at 6 / 12dB Back-off Supporting 2000MHz 5G NR 64-QAM OFDM

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique

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