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Fast and Precise Worst-Case Interference Placement for Shared Cache Analysis

ACM transactions on embedded computing systems, 2016-07, Vol.15 (3), p.1-26

2016

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Falcon: A Graph Manipulation Language for Heterogeneous Systems

ACM transactions on architecture and code optimization, 2016-01, Vol.12 (4), p.1-27

2016

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Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

IEEE transactions on computers, 2014-06, Vol.63 (6), p.1567-1579

2014

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Compiler-assisted power optimization for clustered VLIW architectures

Parallel computing, 2011, Vol.37 (1), p.42-59

2011

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Pragmatic integrated scheduling for clustered VLIW architectures

Software, practice & experience, 2008-03, Vol.38 (3), p.227-257

2008

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Distributed Graph Analytics

Distributed Computing and Internet Technology, p.3-20

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Refining Cache Behavior Prediction Using Cache Miss Paths

ACM transactions on embedded computing systems, 2017-11, Vol.16 (4), p.1-26

2017

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Microarchitecture Sensitive Empirical Models for Compiler Optimizations

Code Generation and Optimization: Proceedings of the International Symposium on Code Generation and Optimization; 11-14 Mar. 2007, 2007, p.131-143

2007

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DH-Falcon: A Language for Large-Scale Graph Processing on Distributed Heterogeneous Systems

2017 IEEE International Conference on Cluster Computing (CLUSTER), 2017, p.439-450

2017

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IR2V EC: LLVM IR Based Scalable Program Embeddings

ACM transactions on architecture and code optimization, 2020-12, Vol.17 (4), p.1-27

2020

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Compiler-assisted energy optimization for clustered VLIW processors

Journal of parallel and distributed computing, 2012-08, Vol.72 (8), p.944-959

2012

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Precise shared cache analysis using optimal interference placement

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014, p.125-134

2014

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Path Sensitive Cache Analysis Using Cache Miss Paths

Verification, Model Checking, and Abstract Interpretation, p.43-60

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A Programmable Hardware Path Profiler

Code Generation and Optimization: Proceedings of the international symposium on Code generation and optimization; 20-23 Mar. 2005, 2005, p.217-228

2005

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Scheduling expression trees for delayed-load architectures

Journal of systems architecture, 2002-12, Vol.48 (4), p.151-173

2002

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Improved Preprocessing Methods for Modulo Scheduling Algorithms

High Performance Computing — HiPC 2002, 2002, p.485-494

2002

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Large Scale Graph Processing in a Distributed Environment

Euro-Par 2017: Parallel Processing Workshops, p.465-477

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Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors

High Performance Computing - HiPC 2006, 2006, p.497-508

2006

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An incremental basic block instruction scheduler

Journal of systems architecture, 1998-11, Vol.45 (3), p.179-203

1998

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WCET estimation for executables in the presence of data caches

International Conference On Embedded Software: Proceedings of the 7th ACM & IEEE international conference on Embedded software; 30 Sept.-03 Oct. 2007, 2007, p.203-212

2007

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Partial redundancy elimination: a simple, pragmatic, and provably correct algorithm

Science of computer programming, 2003-07, Vol.48 (1), p.1-20

2003

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Profiling k-Iteration Paths: A Generalization of the Ball-Larus Profiling Algorithm

2009 International Symposium on Code Generation and Optimization, 2009, p.70-80

2009

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A graph matching based integrated scheduling framework for clustered VLIW processors

Workshops on Mobile and Wireless Networking/High Performance Scientific, Engineering Computing/Network Design and Architecture/Optical Networks Control and Management/Ad Hoc and Sensor Networks/Compil, 2004, p.530-537

2004

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Parallel parsing of arithmetic expressions

IEEE transactions on computers, 1990-01, Vol.39 (1), p.130-132

Srikant, Y.N.

1990

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Implications of Program Phase Behavior on Timing Analysis

2011 15th Workshop on Interaction between Compilers and Computer Architectures, 2011, p.71-79

2011

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Fast and Precise Worst-Case Interference Placement for Shared Cache Analysis

Falcon: A Graph Manipulation Language for Heterogeneous Systems

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

Compiler-assisted power optimization for clustered VLIW architectures

Pragmatic integrated scheduling for clustered VLIW architectures

Distributed Graph Analytics

Refining Cache Behavior Prediction Using Cache Miss Paths

Microarchitecture Sensitive Empirical Models for Compiler Optimizations

DH-Falcon: A Language for Large-Scale Graph Processing on Distributed Heterogeneous Systems

IR2V EC: LLVM IR Based Scalable Program Embeddings

Compiler-assisted energy optimization for clustered VLIW processors

Precise shared cache analysis using optimal interference placement

Path Sensitive Cache Analysis Using Cache Miss Paths

A Programmable Hardware Path Profiler

Scheduling expression trees for delayed-load architectures

Improved Preprocessing Methods for Modulo Scheduling Algorithms

Large Scale Graph Processing in a Distributed Environment

Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors

An incremental basic block instruction scheduler

WCET estimation for executables in the presence of data caches

Partial redundancy elimination: a simple, pragmatic, and provably correct algorithm

Profiling k-Iteration Paths: A Generalization of the Ball-Larus Profiling Algorithm

A graph matching based integrated scheduling framework for clustered VLIW processors

Parallel parsing of arithmetic expressions

Implications of Program Phase Behavior on Timing Analysis

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