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An Exploration into Aphantasia : the Inability to Form Voluntary Mental Imagery

Pounder, Zoë Isabel Emma

2021

Link zum Volltext
ProQuest

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.126-136

2015

Link zum Volltext
IEEE_Xplore

Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.1592-1595

2021

Link zum Volltext
IEEE_Xplore

GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, p.1-9

2022

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IEEE_Xplore

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.235-246

2015

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IEEE_Xplore

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.2556-2560

2022

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IEEE_Xplore

Efficient virtual memory for big memory servers

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.237-248

2013

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NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2020, p.502-514

2020

Link zum Volltext
IEEE_Xplore

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.14-23

2009

Link zum Volltext
IEEE_Xplore

CORUSCANT: Fast Efficient Processing-in-Racetrack Memories

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.784-798

2022

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iDO: compiler-directed failure atomicity for nonvolatile memory

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.258-270

2018

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IEEE_Xplore

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

Link zum Volltext
IEEE_Xplore

CIDAN: Computing in DRAM with Artificial Neurons

2021 IEEE 39th International Conference on Computer Design (ICCD), 2021, p.349-356

2021

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IEEE_Xplore

Disaggregated memory for expansion and sharing in blade servers

Proceedings of the 36th annual international symposium on Computer architecture, 2009, p.267-278

2009

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CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.1-12

2014

Link zum Volltext
IEEE_Xplore

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.385-395

2010

Link zum Volltext
IEEE_Xplore

Filesystem Encryption or Direct-Access for NVM Filesystems? Let's Have Both

2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, p.490-502

2022

Link zum Volltext
IEEE_Xplore

Hydra: A near hybrid memory accelerator for CNN inference

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.1017-1022

2022

Link zum Volltext
IEEE_Xplore

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1182-1197

2021

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PF-DRAM: a precharge-free DRAM structure

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.126-138

2021

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IEEE_Xplore

Gengar: An RDMA-based Distributed Hybrid Memory Pool

2021 IEEE 41st International Conference on Distributed Computing Systems (ICDCS), 2021, p.92-103

2021

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IEEE_Xplore

Characterizing and Modeling Non-Volatile Memory Systems

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, p.496-508

2020

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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.255-268

2017

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Memory-centric system interconnect design with Hybrid Memory Cubes

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013, p.145-155

2013

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IEEE_Xplore

Die Stacking (3D) Microarchitecture

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.469-479

2006

Link zum Volltext
IEEE_Xplore

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An Exploration into Aphantasia : the Inability to Form Voluntary Mental Imagery

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming

GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

Efficient virtual memory for big memory servers

NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

CORUSCANT: Fast Efficient Processing-in-Racetrack Memories

iDO: compiler-directed failure atomicity for nonvolatile memory

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

CIDAN: Computing in DRAM with Artificial Neurons

Disaggregated memory for expansion and sharing in blade servers

CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

Filesystem Encryption or Direct-Access for NVM Filesystems? Let's Have Both

Hydra: A near hybrid memory accelerator for CNN inference

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

PF-DRAM: a precharge-free DRAM structure

Gengar: An RDMA-based Distributed Hybrid Memory Pool

Characterizing and Modeling Non-Volatile Memory Systems

The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

Memory-centric system interconnect design with Hybrid Memory Cubes

Die Stacking (3D) Microarchitecture

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