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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.235-246

2012

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IEEE_Xplore

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.347-357

2009

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IEEE_Xplore

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.43-56

2021

Link zum Volltext
IEEE_Xplore

Chapter 20 What are the differences between long-term, short-term, and working memory?

Progress in Brain Research, 2008, Vol.169, p.323-338

Cowan, Nelson

2008

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Verfügbarkeit prüfen

Transitioning eMRAM from Pilot Project to Volume Production

2023 IEEE International Test Conference (ITC), 2023, p.82-86

2023

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IEEE_Xplore

Neural Effects of Prioritisation on Working Memory

Chekroud, Sammi Ramdane

2022

Link zum Volltext
ProQuest

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.65-76

2010

Link zum Volltext
IEEE_Xplore

An Exploration into Aphantasia : the Inability to Form Voluntary Mental Imagery

Pounder, Zoë Isabel Emma

2021

Link zum Volltext
ProQuest

Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.1592-1595

2021

Link zum Volltext
IEEE_Xplore

Efficient virtual memory for big memory servers

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.237-248

2013

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Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.14-23

2009

Link zum Volltext
IEEE_Xplore

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

Link zum Volltext
IEEE_Xplore

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.385-395

2010

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IEEE_Xplore

Characterizing and Modeling Non-Volatile Memory Systems

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, p.496-508

2020

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Memory-centric system interconnect design with Hybrid Memory Cubes

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013, p.145-155

2013

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IEEE_Xplore

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.72-83

2013

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Does Explicit Memory Interfere with the Implicit Memory of People with Acquired Memory Impairments?

Werrell, Fiona

2020

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ProQuest

Collective Behaviour in Binary Games with Memory

Baldo, Giacomo

2020

Link zum Volltext
ProQuest

Using Sensory Cues to Curate, Study and Support Autobiographical Remembering Across the Lifespan

Woy, A

2020

Link zum Volltext
ProQuest

Computational Associative Memory Powered by Ferroelectric Memory

2023 Device Research Conference (DRC), 2023, p.1-2

2023

Link zum Volltext
IEEE_Xplore

Application-transparent near-memory processing architecture with memory channel network

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.802-814

2018

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IEEE_Xplore

(Almost) Fence-less Persist Ordering

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, p.539-554

2020

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Loose-Ordering Consistency for persistent memory

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.216-223

2014

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IEEE_Xplore

Generalized Data Placement Strategies for Racetrack Memories

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.1502-1507

2020

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IEEE_Xplore

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

Link zum Volltext
IEEE_Xplore

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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

Chapter 20 What are the differences between long-term, short-term, and working memory?

Transitioning eMRAM from Pilot Project to Volume Production

Neural Effects of Prioritisation on Working Memory

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

An Exploration into Aphantasia : the Inability to Form Voluntary Mental Imagery

Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming

Efficient virtual memory for big memory servers

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

Characterizing and Modeling Non-Volatile Memory Systems

Memory-centric system interconnect design with Hybrid Memory Cubes

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Does Explicit Memory Interfere with the Implicit Memory of People with Acquired Memory Impairments?

Collective Behaviour in Binary Games with Memory

Using Sensory Cues to Curate, Study and Support Autobiographical Remembering Across the Lifespan

Computational Associative Memory Powered by Ferroelectric Memory

Application-transparent near-memory processing architecture with memory channel network

(Almost) Fence-less Persist Ordering

Loose-Ordering Consistency for persistent memory

Generalized Data Placement Strategies for Racetrack Memories

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

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