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Prosper: Program Stack Persistence in Hybrid Memory Systems

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.1168-1183

2024

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IEEE_Xplore

EagerReuse: An Efficient Memory Reuse Approach for Complex Computational Graph

2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS), 2023, p.223-229

2023

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IEEE_Xplore

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024, p.583-586

2024

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IEEE_Xplore

Understanding Power Consumption Metric on Heterogeneous Memory Systems

2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS), 2023, p.2859-2862

2023

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IEEE_Xplore

Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM

2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, p.1-7

2024

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IEEE_Xplore

Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.139-155

2024

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IEEE_Xplore

An EEG study to understand semantic and episodic memory retrieval in creative processes

Proceedings of the Design Society, 2024, Vol.4, p.1147-1156

2024

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StreamPIM: Streaming Matrix Computation in Racetrack Memory

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.297-311

2024

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IEEE_Xplore

Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.1141-1153

2024

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IEEE_Xplore

Salus: Efficient Security Support for CXL-Expanded GPU Memory

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.1-15

2024

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IEEE_Xplore

Reliability analysis and mitigation for analog computation-in-memory: from technology to application

2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, p.1-7

2024

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IEEE_Xplore

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.292-294

2024

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IEEE_Xplore

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.186-203

2024

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IEEE_Xplore

A Discovery Platform to Characterize Emerging Nonvolatile Memories for Computing

2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, p.1-5

2024

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IEEE_Xplore

Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.615-615

2024

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IEEE_Xplore

Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.345-360

2024

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IEEE_Xplore

Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024, p.125-128

2024

Link zum Volltext
IEEE_Xplore

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024, p.247-252

2024

Link zum Volltext
IEEE_Xplore

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024, p.241-246

2024

Link zum Volltext
IEEE_Xplore

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.580-582

2024

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IEEE_Xplore

A Closed-Loop Brain-Machine Interface SoC Featuring a 0.2μJ/class Multiplexer Based Neural Network

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.01-02

2024

Link zum Volltext
IEEE_Xplore

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

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Prosper: Program Stack Persistence in Hybrid Memory Systems

EagerReuse: An Efficient Memory Reuse Approach for Complex Computational Graph

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

Understanding Power Consumption Metric on Heterogeneous Memory Systems

Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM

Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory

An EEG study to understand semantic and episodic memory retrieval in creative processes

StreamPIM: Streaming Matrix Computation in Racetrack Memory

Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers

Salus: Efficient Security Support for CXL-Expanded GPU Memory

Reliability analysis and mitigation for analog computation-in-memory: from technology to application

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing

A Discovery Platform to Characterize Emerging Nonvolatile Memories for Computing

Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications

Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System

Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices

A Closed-Loop Brain-Machine Interface SoC Featuring a 0.2μJ/class Multiplexer Based Neural Network

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM

A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs

A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference

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