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A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

IEEE transactions on very large scale integration (VLSI) systems, 2015-07, Vol.23 (7), p.1281-1286

2015

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Architectural Advancement of Digital Low-Dropout Regulators

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Capacitorless Self-Clocked All-Digital Low-Dropout Regulator

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.266-276

2019

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Output-Capacitorless Tri-Loop Digital Low Dropout Regulator Achieving 99.91% Current Efficiency and 2.87 fs FOM

IEEE transactions on power electronics, 2021-02, Vol.36 (2), p.2044-2058

2021

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Capacitor-Less Dual-Mode All-Digital LDO With ΔΣ-Modulation-Based Ripple Reduction

IEEE transactions on circuits and systems. II, Express briefs, 2021-05, Vol.68 (5), p.1620-1624

2021

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A CMOS self-regulating VCO with low supply sensitivity

IEEE journal of solid-state circuits, 2004-01, Vol.39 (1), p.42-48

2004

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A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1414-1420

2002

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A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition

IEEE journal of solid-state circuits, 2001-10, Vol.36 (10), p.1574-1581

2001

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A 0.236 mm ^, 3.99 mW Fully Integrated 90 nm CMOS L1/L5 GPS Frequency Synthesizer Using a Regulated Ring VCO

IEEE microwave and wireless components letters, 2012-06, Vol.22 (6), p.324-326

Hwang, In-Chul

2012

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A VLSI chip for isolated speech recognition system

IEEE transactions on consumer electronics, 1996-08, Vol.42 (3), p.458-467

1996

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A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1414-1420

2002

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Double precharge TSPC for high-speed dual-modulus prescaler

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.609-612

1999

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A self-regulating VCO with supply sensitivity of <0.15%-delay/1%-supply

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.140-453 vol.1

2002

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Low-power small-area /spl plusmn/7.28 ps jitter 1 GHz DLL-based clock generator

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.142-453 vol.1

2002

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Low-power small-area /spl plusmn/7.28ps jitter 1GHz DLL-based clock generator

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.106-423

2002

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An LPC cepstrum processor for speech recognition

1998 IEEE International Symposium on Circuits and Systems (ISCAS), 1998, Vol.4, p.233-236 vol.4

1998

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A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

Architectural Advancement of Digital Low-Dropout Regulators

Capacitorless Self-Clocked All-Digital Low-Dropout Regulator

Output-Capacitorless Tri-Loop Digital Low Dropout Regulator Achieving 99.91% Current Efficiency and 2.87 fs FOM

Capacitor-Less Dual-Mode All-Digital LDO With ΔΣ-Modulation-Based Ripple Reduction

A CMOS self-regulating VCO with low supply sensitivity

A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator

A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition

A 0.236 mm ^, 3.99 mW Fully Integrated 90 nm CMOS L1/L5 GPS Frequency Synthesizer Using a Regulated Ring VCO

A VLSI chip for isolated speech recognition system

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

Double precharge TSPC for high-speed dual-modulus prescaler

A self-regulating VCO with supply sensitivity of <0.15%-delay/1%-supply

Low-power small-area /spl plusmn/7.28 ps jitter 1 GHz DLL-based clock generator

Low-power small-area /spl plusmn/7.28ps jitter 1GHz DLL-based clock generator

An LPC cepstrum processor for speech recognition

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