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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Foreword

Solid-state electronics, 2011-05, Vol.59 (1), p.1

2011

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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Experimental developments of A2RAM memory cells on SOI and bulk substrates

Solid-state electronics, 2015-01, Vol.103, p.7-14

2015

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Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

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Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Solid-state electronics, 2011-11, Vol.65-66, p.94-102

2011

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Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Solid-state electronics, 2016-11, Vol.125, p.175-181

2016

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SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Solid-state electronics, 2011-11, Vol.65-66, p.256-262

2011

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Papers Selected from the EUROSOI 2010 Conference

Solid-state electronics, 2011, Vol.59 (1)

2011

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Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

Microelectronic engineering, 2011-07, Vol.88 (7), p.1276-1279

2011

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Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances

Solid-state electronics, 2013-12, Vol.90, p.143-148

2013

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Foreword

Solid-state electronics, 2007-02, Vol.51 (2), p.187

2007

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A systematic investigation of work function in advanced metal gate-HfO2-SiO2 structures with bevel oxide

Solid-state electronics, 2007-11, Vol.51 (11-12), p.1515-1522

2007

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EUROSOI'06 Conference. Selected papers

Solid-state electronics, 2007, Vol.51 (2)

2007

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A systematic investigation of work function in advanced metal gate–HfO 2–SiO 2 structures with bevel oxide

Solid-state electronics, 2007, Vol.51 (11), p.1515-1522

2007

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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Electrical characterization of stacked SOI nanowires at low temperatures

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Foreword

Analog characteristics of n-type vertically stacked nanowires

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Experimental developments of A2RAM memory cells on SOI and bulk substrates

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Electrical characterization of vertically stacked p-FET SOI nanowires

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Papers Selected from the EUROSOI 2010 Conference

Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances

Foreword

A systematic investigation of work function in advanced metal gate-HfO2-SiO2 structures with bevel oxide

EUROSOI'06 Conference. Selected papers

A systematic investigation of work function in advanced metal gate–HfO 2–SiO 2 structures with bevel oxide

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