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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2326-2336

2011

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IEEE_Xplore

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2355-2362

2007

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IEEE_Xplore

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

2012 Symposium on VLSI Technology (VLSIT), 2012, p.113-114

2012

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IEEE_Xplore

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2473-2482

2011

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024-06, p.1-1

2024

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Foreword

Solid-state electronics, 2011-05, Vol.59 (1), p.1

2011

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

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IEEE_Xplore

Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.1161-1167

2014

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IEEE_Xplore

Experimental developments of A2RAM memory cells on SOI and bulk substrates

Solid-state electronics, 2015-01, Vol.103, p.7-14

2015

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Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

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Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

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Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.969-975

2014

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IEEE_Xplore

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Solid-state electronics, 2016-11, Vol.125, p.175-181

2016

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Benefits and challenges of FDSOI technology for 14nm node

IEEE 2011 International SOI Conference, 2011, p.1-21

Faynot, O.

2011

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IEEE_Xplore

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Electrical characterization of stacked SOI nanowires at low temperatures

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Foreword

Analog characteristics of n-type vertically stacked nanowires

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

Experimental developments of A2RAM memory cells on SOI and bulk substrates

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Electrical characterization of vertically stacked p-FET SOI nanowires

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Benefits and challenges of FDSOI technology for 14nm node

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