UB Paderborn / Katalog / Suche / in CDI

VLSI Physical Design: From Graph Partitioning to Timing Closure

Second edition., 2022

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Limits on fundamental limits to computation

Nature (London), 2014-08, Vol.512 (7513), p.147-154

Markov, Igor L

2014

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Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

Second edition., 2016

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Electronic Design Automation for IC System Design, Verification, and Testing

Second edition., 2016

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Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-06, Vol.34 (6), p.961-971

2015

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Simulating Quantum Computation by Contracting Tensor Networks

SIAM journal on computing, 2008-01, Vol.38 (3), p.963-981

2008

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Progress and Challenges in VLSI Placement Research

Proceedings of the IEEE, 2015-11, Vol.103 (11), p.1985-2003

2015

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Ending Piracy of Integrated Circuits

Computer (Long Beach, Calif.), 2010-10, Vol.43 (10), p.30-38

2010

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Personalization for web-based services using offline reinforcement learning

Machine learning, 2024-05, Vol.113 (5), p.3049-3071

2024

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SimPL: An Effective Placement Algorithm

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-01, Vol.31 (1), p.50-60

2012

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Simulation of Quantum Circuits via Stabilizer Frames

IEEE transactions on computers, 2015-08, Vol.64 (8), p.2323-2336

2015

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Detecting Qubit-coupling Faults in Ion-trap Quantum Computers

2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, p.387-399

2022

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Assembling 2-D Blocks Into 3-D Chips

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-02, Vol.31 (2), p.228-241

2012

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Fixed-outline floorplanning: enabling hierarchical design

IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.1120-1135

2003

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A layered software architecture for quantum computing design tools

Computer (Long Beach, Calif.), 2006-01, Vol.39 (1), p.74-83

2006

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Obstacle-Aware Clock-Tree Shaping During Placement

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-02, Vol.31 (2), p.205-216

2012

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Constant-Degree Graph Expansions that Preserve Treewidth

Algorithmica, 2011-04, Vol.59 (4), p.461-470

2011

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Signature-Based SER Analysis and Design of Logic Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-01, Vol.28 (1), p.74-86

2009

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Impact of Future Technologies on Architecture

IEEE MICRO, 2016-07, Vol.36 (4), p.48-56

2016

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Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

IEEE MICRO, 2011-07, Vol.31 (4), p.51-62

2011

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Large-scale Boolean matching

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010, p.771-776

2010

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Faster Schrödinger-style simulation of quantum circuits

2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, p.194-207

2021

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Fine Control of Local Whitespace in Placement

VLSI Design, 2008, Vol.2008 (1)

2008

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Error-correction and crosstalk avoidance in DSM busses

IEEE transactions on very large scale integration (VLSI) systems, 2004-10, Vol.12 (10), p.1076-1080

2004

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Automating Postsilicon Debugging and Repair

Computer (Long Beach, Calif.), 2008-07, Vol.41 (7), p.47-54

2008

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VLSI Physical Design: From Graph Partitioning to Timing Closure

Limits on fundamental limits to computation

Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

Electronic Design Automation for IC System Design, Verification, and Testing

Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking

Simulating Quantum Computation by Contracting Tensor Networks

Progress and Challenges in VLSI Placement Research

Ending Piracy of Integrated Circuits

Personalization for web-based services using offline reinforcement learning

SimPL: An Effective Placement Algorithm

Simulation of Quantum Circuits via Stabilizer Frames

Detecting Qubit-coupling Faults in Ion-trap Quantum Computers

Assembling 2-D Blocks Into 3-D Chips

Fixed-outline floorplanning: enabling hierarchical design

A layered software architecture for quantum computing design tools

Obstacle-Aware Clock-Tree Shaping During Placement

Constant-Degree Graph Expansions that Preserve Treewidth

Signature-Based SER Analysis and Design of Logic Circuits

Impact of Future Technologies on Architecture

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

Large-scale Boolean matching

Faster Schrödinger-style simulation of quantum circuits

Fine Control of Local Whitespace in Placement

Error-correction and crosstalk avoidance in DSM busses

Automating Postsilicon Debugging and Repair

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