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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-06, Vol.11 (11)

2022

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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248-1252

2023

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A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

Electronics (Basel), 2024-07, Vol.13 (13), p.2638

2024

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A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

2013

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A 0.1–2.75 GHz high-linear low-noise transconductance amplifier for high-performance multi-standard wireless applications

Microsystem technologies : sensors, actuators, systems integration, 2020-07, Vol.26 (7), p.2279-2293

2020

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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Analog integrated circuits and signal processing, 2013-12, Vol.77 (3), p.567-582

2013

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A 0.1-40 GHz broadband MEMS clamped-clamped beam capacitive power sensor based on GaAs technology

Journal of micromechanics and microengineering, 2014-06, Vol.24 (6), p.65024-7

2014

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A 0-1 bat algorithm for cellular network optimisation: a systematic study on mapping techniques

International journal of reasoning-based intelligent systems, 2017, Vol.9 (1), p.22

2017

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{0,1}-Brauer Configuration Algebras and Their Applications in Graph Energy Theory

Mathematics (Basel), 2021-12, Vol.9 (23), p.3042

2021

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A 0-1 Integer LP Formulation for Real Time Optimization of Traffic Signal Control

2009 International Conference on Measuring Technology and Mechatronics Automation, 2009, Vol.3, p.423-426

2009

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0-1 Integer Programming Based on DNA Tetrahedral Probe

Computational Intelligence and Intelligent Systems, p.91-100

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0-1 Integer Programming for Generation Maintenance Scheduling in Power Systems Based on Teaching Learning Based Optimization (TLBO)

Contemporary Computing, Vol.306, p.53-63

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0‐1 Knapsack problem driven resource scheduling in caching‐enabled network: A case study on sports video

Internet technology letters, 2021-09, Vol.4 (5), p.n/a

Xu, Qiang

2021

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0/1 Knapsack Problem using Diversity based Dual Population Genetic Algorithm

International journal of intelligent systems and applications, 2014-09, Vol.6 (10), p.34-40

2014

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(0, 1)-Matrix Completion, Majorization, and Their Applications in Smart Grids

Mo, Yanfang

2019

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0 + 1 = talk

Summit, 2002-12, Vol.5 (4), p.6

Bray, Richard

2002

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A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip

IEEE International SOC Conference, 2004. Proceedings, 2004, p.141-142

2004

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0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

Electronics (Basel), 2020-01, Vol.9 (1), p.133

2020

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A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

Journal of semiconductors, 2011-10, Vol.32 (10), p.105005

2011

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A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

International journal of electronics, 2014-02, Vol.101 (2), p.182-193

2014

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A 0.15-μm CMOS baseband LSI employing sleep mode with clock-offset compensation for M2M wireless sensor networks

IEEJ transactions on electrical and electronic engineering, 2015-09, Vol.10 (5), p.576-584

2015

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0.18 micrometers CMOS piezoelectric impedance-based structural health monitoring integrated circuit design

Wang, Shirui

2010

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A 0.18- mu hbox m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

IEEE transactions on microwave theory and techniques, 2011-01, Vol.59 (1), p.116-124

2011

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A 0.18 mum CMOS direct down-converter for highly integrated 3G receivers

Analog integrated circuits and signal processing, 2007-10, Vol.53 (1), p.35-42

2007

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A 0.18μm CMOS voltage multiplier arrangement for RF energy harvesting

Analog integrated circuits and signal processing, 2017-09, Vol.92 (3), p.343-353

2017

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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

A 0.1–2.75 GHz high-linear low-noise transconductance amplifier for high-performance multi-standard wireless applications

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1-40 GHz broadband MEMS clamped-clamped beam capacitive power sensor based on GaAs technology

A 0-1 bat algorithm for cellular network optimisation: a systematic study on mapping techniques

{0,1}-Brauer Configuration Algebras and Their Applications in Graph Energy Theory

A 0-1 Integer LP Formulation for Real Time Optimization of Traffic Signal Control

0-1 Integer Programming Based on DNA Tetrahedral Probe

0-1 Integer Programming for Generation Maintenance Scheduling in Power Systems Based on Teaching Learning Based Optimization (TLBO)

0‐1 Knapsack problem driven resource scheduling in caching‐enabled network: A case study on sports video

0/1 Knapsack Problem using Diversity based Dual Population Genetic Algorithm

(0, 1)-Matrix Completion, Majorization, and Their Applications in Smart Grids

0 + 1 = talk

A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip

0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A 0.15-μm CMOS baseband LSI employing sleep mode with clock-offset compensation for M2M wireless sensor networks

0.18 micrometers CMOS piezoelectric impedance-based structural health monitoring integrated circuit design

A 0.18- mu hbox m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

A 0.18 mum CMOS direct down-converter for highly integrated 3G receivers

A 0.18μm CMOS voltage multiplier arrangement for RF energy harvesting

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