Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
DC-16 GHz GaAs track-and-hold amplifier using sampling rate and linearity enhancement techniques
Ist Teil von
Electronics letters, 2018-01, Vol.54 (2), p.83-85
Ort / Verlag
The Institution of Engineering and Technology
Erscheinungsjahr
2018
Link zum Volltext
Quelle
Wiley Online Library
Beschreibungen/Notizen
A DC-16 GHz track-and-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-and-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of −45 dB.