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A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture
International journal of circuit theory and applications, 2017-04, Vol.45 (4), p.466-482
Kim, Yeomyung
Shon, Doohyun
Kim, Tae Wook
2017
Details
Autor(en) / Beteiligte
Kim, Yeomyung
Shon, Doohyun
Kim, Tae Wook
Titel
A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture
Ist Teil von
International journal of circuit theory and applications, 2017-04, Vol.45 (4), p.466-482
Erscheinungsjahr
2017
Link zum Volltext
Quelle
Wiley-Blackwell Journals
Beschreibungen/Notizen
Summary This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd. This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB.
Sprache
Englisch
Identifikatoren
ISSN: 0098-9886
eISSN: 1097-007X
DOI: 10.1002/cta.2272
Titel-ID: cdi_wiley_primary_10_1002_cta_2272_CTA2272
Format
–
Schlagworte
analog‐to‐digital converter
,
compact TDC
,
double‐gain‐boosting current source
,
dual‐slope architecture
,
interpolator
,
time‐to‐digital converter
,
time‐to‐voltage converter
,
voltage domain TDC
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