Details

Autor(en) / Beteiligte

• Garvey, J.
• Hillier, S.
• Mahout, G.
• Staley, R.
• Watkins, P.
• Watson, A.
• Achenbach, R.
• Hanke, P.
• Hinderer, W.
• Kaiser, D.
• Kluge, E.-E.
• Meier, K.
• Nix, O.
• Penno, K.
• Schmitt, K.
• Bauss, B.
• Dahlhoff, A.
• Jakobs, K.
• Mahboubi, K.
• Schäfer, U.
• Thomas, J.
• Trefzger, T.
• Eisenhandler, E.
• Landon, M.P.J.
• Mills, D.
• Moyse, E.
• Apostologlou, P.
• Barnett, B.M.
• Brawn, I.P.
• Davis, A.O.
• Edwards, J.
• Gee, C.N.P.
• Gillman, A.R.
• Hatley, R.
• Perera, V.J.O.
• Bohm, C.
• Hellman, S.
• Silverstein, S.B.

Titel

Use of an FPGA to identify electromagnetic clusters and isolated hadrons in the ATLAS level-1 calorimeter trigger

Ist Teil von

• Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2003-10, Vol.512 (3), p.506-516

Ort / Verlag

Elsevier B.V

Erscheinungsjahr

2003

Link zum Volltext

Quelle

Elsevier ScienceDirect Journals Complete

Beschreibungen/Notizen

• At the full LHC design luminosity of 10 34 cm −2 s −1 , there will be approximately 10 9 proton–proton interactions per second. The ATLAS level-1 trigger is required to have an acceptance factor of ∼10 −3. The calorimeter trigger covers the region | η|⩽5.0, and φ=0 to 2 π. The distribution of transverse energy over the trigger phase space is analysed to identify candidates for electrons/photons, isolated hadrons, QCD jets and non-interacting particles. The Cluster Processor of the level-1 calorimeter trigger is designed to identify transverse energy clusters associated with the first two of these. The algorithms based on the trigger tower energies which have been designed to identify such clusters, are described here. The algorithms are evaluated using an FPGA. The reasons for the choice of the actual FPGA being used are given. The performance of the FPGA has been fully simulated, and the expected latency has been shown to be within the limits of the time allocated to the cluster trigger. These results, together with the results of measurements made with real data into a fully configured FPGA, are presented and discussed.