Details

Autor(en) / Beteiligte

• Patranabis, Sikhar
• Chakraborty, Abhishek
• Nguyen, Phuong Ha
• Mukhopadhyay, Debdeep

Titel

A Biased Fault Attack on the Time Redundancy Countermeasure for AES

Ist Teil von

• Constructive Side-Channel Analysis and Secure Design, p.189-203

Ort / Verlag

Cham: Springer International Publishing

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• In this paper we propose the first practical fault attack on the time redundancy countermeasure for AES using a biased fault model. We develop a scheme to show the effectiveness of a biased fault model in the analysis of the time redundancy countermeasure. Our attack requires only faulty ciphertexts and does not assume strong adversarial powers. We successfully demonstrate our attack on simulated data and 128-bit time redundant AES implemented on Xilinx Spartan-3A FPGA.