Details

Autor(en) / Beteiligte

• Farjad-Rad, R
• Yang, C-K K
• Horowitz, M A
• Lee, T H

Titel

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Ist Teil von

• IEEE journal of solid-state circuits, 1999-05, Vol.34 (5), p.580-585

Erscheinungsjahr

1999

Link zum Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A serial link transmitter fabricated in a large-scale integrated 0.4-mum CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height > 350 mV and a width > 100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5x2.0 mm(2) of die area