Details

Autor(en) / Beteiligte

• HSU, Sheng-Fu
• KER, Ming-Dou

Titel

Transient-Induced Latchup Dependence on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits

Ist Teil von

• IEEE transactions on electron devices, 2007-08, Vol.54 (8), p.2002-2010

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2007

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• The bipolar (underdamped sinusoidal) transient noise on power pins of CMOS integrated circuits (ICs) can trigger latchup in CMOS ICs under system-level electrostatic-discharge test. Two dominant parameters of bipolar transient noise-damping frequency and damping factor-strongly depend on system shielding, board-level noise filter, chip-/board-level layout, etc. The transient-induced-latchup (TLU) dependence on power-pin damping frequency and damping factor was characterized by device simulation and verified by experimental measurement. From the simulation results, bipolar-trigger waveforms with damping frequencies of several tens of megahertz can trigger the TLU most easily. However, TLU is less sensitive to the bipolar-trigger waveforms with an excessively large damping factor or an excessively low/high damping frequency. The simulation results have been experimentally verified with the silicon-controlled-rectifier (SCR) test structures that are fabricated in a 0.25-mum CMOS technology.