IEEE transactions on electron devices, 2011-06, Vol.58 (6), p.1597-1607
2011
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Details
- Autor(en) / Beteiligte
- Titel
- Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines
- Ist Teil von
- IEEE transactions on electron devices, 2011-06, Vol.58 (6), p.1597-1607
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2011
- Quelle
- IEEE Xplore Digital Library
- Beschreibungen/Notizen
- In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9383eISSN: 1557-9646DOI: 10.1109/TED.2011.2123100Titel-ID: cdi_proquest_miscellaneous_889444389
- Format
- –
- Schlagworte
- Applied sciences, Design. Technologies. Operation analysis. Testing, Devices, Electronics, Exact sciences and technology, Extremely thin SOI (ETSOI), FinFET, FinFETs, Guidelines, implant-free process, Integrated circuits, Integrated circuits by function (including memories and processors), Intermediate frequency, Ion implantation, ion implantation and system-on-chip (SoC), Leakage current, Molecular electronics, nanoelectronics, Nanocomposites, Nanomaterials, Nanostructure, Optimization, Performance evaluation, process co-optimization, scaling, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Solid modeling, System on chip, System-on-a-chip, Transistors