Details

Autor(en) / Beteiligte

• Wei-Chung Kao
• Wei-Shun Chuang
• Hsiu-Ting Lin
• Li, J.C.-M.
• Manquinho, V.

Titel

DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.392-400

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2010

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This paper presents a design for testability and minimum leakage pattern generation technique to reduce static power during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cells.