Details

Autor(en) / Beteiligte

• Blatchford, Jim
• Prins, Steve
• Dam, Thuc
• Pang, Linyong

Titel

Improving 22nm design space with source/design optimization

Ist Teil von

• Solid state technology, 2010-06, Vol.53 (6), p.36-37

Ort / Verlag

Tulsa: PennWell Publishing Corp

Erscheinungsjahr

2010

Beschreibungen/Notizen

• The 22nm logic node is unprecedented in that it must be realized without the benefit of enabling lithographic exposure tool, so that double -patterning (DP) techniques must be invoked to achieve the resolution requirements. To avoid the potentially high wafer cost associated with extensive use of DP techniques, there is a strong drive to determine design rules for back-end-of-the-line (BEOL) metal and via levels that allow these layers to be manufactured with a single lithographic exposure (SE) per layer.