Details

Autor(en) / Beteiligte

• Fukutome, H.
• Hosaka, K.
• Kawamura, K.
• Ohta, H.
• Uchino, Y.
• Akiyama, S.
• Aoyama, T.

Titel

Sub-30-nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process

Ist Teil von

• IEEE electron device letters, 2008-07, Vol.29 (7), p.765-767

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2008

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE

Beschreibungen/Notizen

• We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents of 25-nm D-FUSI CMOS transistors increased by 15% more than those of the control.