Details

Autor(en) / Beteiligte

• GHERMAN, V
• WUNDERLICH, H.-J
• SCHLOEFFEL, J
• GARBERS, M

Titel

Deterministic logic BIST for transition fault testing

Ist Teil von

• IET computers & digital techniques, 2007-05, Vol.1 (3), p.180-186

Ort / Verlag

Stevenage: Institution of Engineering and Technology

Erscheinungsjahr

2007

Beschreibungen/Notizen

• Built-in self-test (BIST) is an attractive approach to detect delay faults, because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, the authors consider the so-called transition fault model, which is widely used for complexity reasons, and an extension of a DLBIST scheme for transition fault testing is presented. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using difficult-to-test industrial designs.