Details

Autor(en) / Beteiligte

• Farrell, J.A.
• Fischer, T.C.

Titel

Issue logic for a 600-MHz out-of-order execution microprocessor

Ist Teil von

• IEEE journal of solid-state circuits, 1998-05, Vol.33 (5), p.707-712

Ort / Verlag

IEEE

Erscheinungsjahr

1998

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.