Details

Autor(en) / Beteiligte

• Gupta, Sumit
• Gupta, Rajesh Kumar
• Dutt, Nikil D
• Nicolau, Alexandru

Titel

Coordinated parallelizing compiler optimizations and high-level synthesis

Ist Teil von

• ACM transactions on design automation of electronic systems, 2004-10, Vol.9 (4), p.441-470

Ort / Verlag

New York: Association for Computing Machinery

Erscheinungsjahr

2004

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the SPARK framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.