Details

Autor(en) / Beteiligte

• Vangal, S
• Anders, M A
• Borkar, N
• Seligman, E
• Govindarajulu, V
• Erraguntla, V
• Wilson, H
• Pangal, A
• Veeramachaneni, V
• Tschanz, J W
• Ye, Y
• Somasekhar, D
• Bloechel, B A
• Dermer, G E
• Krishnamurthy, R K
• Soumyanath, K
• Mathew, S
• Narendra, S G
• Stan, M R

Titel

5-GHz 32-bit integer execution core in 130-nm dual-V/T/ CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421-1432

Erscheinungsjahr

2002

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry x 2 ALU instruction scheduler loop and a 32-entry x 32-bit register file is described. In a 130 nm six-metal, dual-V/T/ CMOS technology, the 2.3 mm(2) prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25 deg C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25 deg C.