IEEE MICRO, 2006-03, Vol.26 (2), p.10-24
2006
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Details
- Autor(en) / Beteiligte
- Titel
- Synergistic Processing in Cell's Multicore Architecture
- Ist Teil von
- IEEE MICRO, 2006-03, Vol.26 (2), p.10-24
- Ort / Verlag
- Los Alamitos: IEEE
- Erscheinungsjahr
- 2006
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. The streamlined architecture provides an efficient multithreaded execution environment for both scalar and SIMD threads and represents a reaffirmation of the RISC principles of combining leading edge architecture and compiler optimizations. These design decisions have enabled the Cell BE to deliver unprecedented supercomputer-class compute power for consumer applications
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0272-1732eISSN: 1937-4143DOI: 10.1109/MM.2006.41Titel-ID: cdi_proquest_miscellaneous_28849431
- Format
- –
- Schlagworte
- Architecture, Boundary element method, Broadband, Cell Broadband Engine, Computer architecture, Cost function, Data paths, Design optimization, Engines, Investments, Mathematical analysis, Microprocessors, multicore architecture, Multicore processing, Optimization, Parallel processing, Pipelines, Programming profession, Scalars, synergistic processing, Technological innovation