Details

Autor(en) / Beteiligte

• Jung-Suk Goo
• Qi Xiang
• Takamura, Y.
• Haihong Wang
• Pan, J.
• Arasnia, F.
• Paton, E.N.
• Besser, P.
• Sidorov, M.V.
• Adem, E.
• Lochtefeld, A.
• Braithwaite, G.
• Currie, M.T.
• Hammond, R.
• Bulsara, M.T.
• Ming-Ren Lin

Titel

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Ist Teil von

• IEEE electron device letters, 2003-05, Vol.24 (5), p.351-353

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2003

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.