Details

Autor(en) / Beteiligte

• Franch, R L
• Dhong, S H
• Scheuerlein, R E

Titel

A large < e1 > V < /e1 > (DS) data retention test pattern forDRAM' s

Ist Teil von

• IEEE journal of solid-state circuits, 1992-08, Vol.27 (8), p.1214-1217

Erscheinungsjahr

1992

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• A test pattern for testing DRAM cell data retention that differs from conventional retention time tests is described. The test pattern is applicable to non- < e1 > V < /e1 > (DD) bit-line precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case < e1 > V < /e1 > (DS) across them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern's effectiveness in screening subthreshold leakage