IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.133-137
1993
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Details
- Autor(en) / Beteiligte
- Titel
- A clock feedthrough reduction circuit for switched-current systems
- Ist Teil von
- IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.133-137
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 1993
- Quelle
- IEEE Electronic Library (IEL)
- Beschreibungen/Notizen
- A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 mu m CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%.< >
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/4.192044Titel-ID: cdi_proquest_miscellaneous_28208499
- Format
- –
- Schlagworte
- Applied sciences, Capacitance, Circuit testing, Clocks, CMOS process, Design. Technologies. Operation analysis. Testing, Electronics, Exact sciences and technology, Frequency, Integrated circuits, Semiconductor device modeling, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Solid modeling, Student members, Switching circuits, Voltage