Details

Autor(en) / Beteiligte

• Hara, H
• Sakurai, T
• Nagamatsu, T
• Seta, K
• Momose, H
• Niitsu, Y
• Miyakawa, H
• Matsuda, K
• Watanabe, Y
• Sano, F
• Chiba, A

Titel

0.5-mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

Ist Teil von

• IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1579-1584

Erscheinungsjahr

1992

Link zum Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

• BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-mum BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip