Details

Autor(en) / Beteiligte

• Hoenigschmid, H
• Frey, A
• DeBrosse, J K
• Kirihata, T
• Mueller, G
• Storaska, D W
• Daniel, G
• Frankowsky, G
• Guay, K P
• Hanson, D R
• Hsu, L L-C
• Ji, B
• Netis, D G
• Panaroni, S
• Radens, C
• Reith, A M
• Terletzki, H
• Weinfurtner, O
• Alsmeier, J

Titel

A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

Ist Teil von

• IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

Erscheinungsjahr

2000

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• A 7F(2) DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 mum technology. This concept features an advanced 30 deg tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip