Details

Autor(en) / Beteiligte

• Pei-Jer Tzeng
• Maikap, S.
• Peng-Shiu Chen
• Yu-Wei Chou
• Chieh-Shuo Liang
• Lurng-Shehng Lee

Titel

Physical and reliability characteristics of Hf-based gate dielectrics on strained-Si/sub 1-x/Ge/sub x/ MOS devices

Ist Teil von

• IEEE transactions on device and materials reliability, 2005-06, Vol.5 (2), p.168-176

Ort / Verlag

IEEE

Erscheinungsjahr

2005

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• The physical and reliability characteristics of strained-Si/sub 0.8/Ge/sub 0.2/ MOS capacitor and strained-Si/sub 0.7/Ge/sub 0.3/ MOSFET with Hf-based gate dielectrics prepared by atomic layer chemical vapor deposition are investigated. The thickness and composition of the gate dielectrics are measured by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, respectively. The gate leakage current and interface traps of HfO/sub 2//Si/sub 1-x/Ge/sub x/ gate structure are slightly higher as compared to the HfO/sub 2//Si MOS devices, which is basically caused by the Ge at the interface. The electrical properties of both HfO/sub 2//Si and HfO/sub 2//Si/sub 1-x/Ge/sub x/ devices can be improved with increasing PDA temperature up to 800/spl deg/C, which is due to the thicker interfacial layer grown at the interface, even though crystallization also grows with increasing temperature. However, with higher PDA temperature (>800/spl deg/C), serious crystallization of HfO/sub 2/ film causes more bulk traps induced electrical degradation. The electrical stress induced degradation of Si/sub 1-x/Ge/sub x/ substrate is slightly higher as compared to the control Si, due to more traps generations at the HfO/sub 2//Si/sub 1-x/Ge/sub x/ interface. For MOSFET, strained-Si/sub 1-x/Ge/sub x/ can effectively improve the drain current for about 20% at saturation and 69% at linear region. The higher gate leakage (J/sub g//spl sim/1.4/spl times/10/sup -9/A/cm/sup 2/ at 2 V) and lower breakdown voltage (BD/spl sim/3.1 V) of Si/sub 0.7/Ge/sub 0.3/ pMOS devices are observed as compared to control Si devices (J/sub g//spl sim/7.9/spl times/10/sup -12/A/cm/sup 2/ at 2 V and BD/spl sim/7.4 V). After the electrical stress, the degradation of drain current and transconductance and the shift of threshold voltage for Si/sub 1-x/Ge/sub x/ PMOSFET are larger than those for control Si devices, implying Ge induced trap generation at the Hf-silicate/Si/sub 1-x/Ge/sub x/ interface.