Details

Autor(en) / Beteiligte

• Seo, Seunghwan
• Cho, Jeong‐Ick
• Jung, Kil‐Su
• Andreev, Maksim
• Lee, Ju‐Hee
• Ahn, Hogeun
• Jung, Sooyoung
• Lee, Taeran
• Kim, Byeongchan
• Lee, Seojoo
• Kang, Juncheol
• Lee, Kyeong‐Bae
• Lee, Ho‐Jun
• Kim, Ki Seok
• Yeom, Geun Young
• Heo, Keun
• Park, Jin‐Hong

Titel

A Van Der Waals Reconfigurable Multi‐Valued Logic Device and Circuit Based on Tunable Negative‐Differential‐Resistance Phenomenon

Ist Teil von

• Advanced materials (Weinheim), 2022-09, Vol.34 (36), p.e2202799-n/a

Ort / Verlag

Weinheim: Wiley Subscription Services, Inc

Erscheinungsjahr

2022

Quelle

Wiley-Blackwell Journals

Beschreibungen/Notizen

• Multi‐valued logic (MVL) technology that utilizes more than two logic states has recently been reconsidered because of the demand for greater power saving in current binary logic systems. Extensive efforts have been invested in developing MVL devices with multiple threshold voltages by adopting negative differential transconductance and resistance. In this study, a reconfigurable, multiple negative‐differential‐resistance (m‐NDR) device with an electric‐field‐induced tunability of multiple threshold voltages is reported, which comprises a BP/ReS2 heterojunction and a ReS2/h‐BN/metal capacitor. Tunability for the m‐NDR phenomenon is achieved via the resistance modulation of the ReS2 layer by electrical pulses applied to the capacitor region. Reconfigurability is verified in terms of the function of an MVL circuit composed of a reconfigurable m‐NDR device and a load transistor, wherein staggered‐type and broken‐type double peak‐NDR device operations are adopted for ternary inverter and latch circuits, respectively. A reconfigurable, multiple negative‐differential‐resistance device with an electric‐field‐induced tunability of multiple threshold voltages is proposed. Following the successful verification of the tunability of multiple negative‐differential‐resistance phenomenon, the reconfigurability in terms of the function of multi‐valued logic circuits, from ternary inverter to latch circuit, is demonstrated.