Details

Autor(en) / Beteiligte

• Watanabe, N.
• Morishita, F.
• Taito, Y.
• Yamazaki, A.
• Tanizaki, T.
• Dosaka, K.
• Morooka, Y.
• Igaue, F.
• Furue, K.
• Nagura, Y.
• Komoike, T.
• Morihara, T.
• Hachisuka, A.
• Arimoto, K.
• Ozaki, H.

Titel

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Ist Teil von

• 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.388-389

Ort / Verlag

IEEE

Erscheinungsjahr

2001

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TAT) for the various specifications, as well as lower-voltage operation. Conventional eDRAM is generated by placement of hardware macros that are designed beforehand. The hardware macro restricts eDRAM specifications, and many hardware macros are necessary to support the demands of different customers. An eDRAM architecture that provides only the interface component as a software macro, i.e., hardware description language (HDL), has been recently reported. However, in this architecture, adjusting of control signal delays and differing control circuits are necessary for each memory configuration. The architecture reported here provides reduction of design TAT, more than 120 k eDRAM configurations, 1.2 V (100 MHz) to 1.8 V (200 MHz) operation, and a flexible interface. In addition, an enhanced on-chip tester tests the various eDRAM macros, reducing test time to 1/64 with a simultaneous 512 b I/O pass/failjudgment, and performs repair analysis at speed testing conditions.