Details

Autor(en) / Beteiligte

• Schreutelkamp, R.J.
• Vandenabeele, P.
• Deweerdt, B.
• Verbeeck, R.
• Maex, K.

Titel

Two-step anneals to avoid bridging during Co silicidation

Ist Teil von

• Applied surface science, 1993-01, Vol.73, p.162-166

Ort / Verlag

Amsterdam: Elsevier B.V

Erscheinungsjahr

1993

Quelle

Elsevier Journal Backfiles on ScienceDirect (DFG Nationallizenzen)

Beschreibungen/Notizen

• A two-step rapid thermal process has successfully been applied for the simultaneous Co silicidation of source/drain and gate areas in MOS test structures while avoiding lateral creep or bridging. The method is based on the formation of CoSi on the active areas and poly-Si gate lines during the first RTP step, while keeping the thermal budget sufficiently low in order not to form this silicide phase on the spacers. Following a selective etch, a second RTP step leads to the formation of CoSi 2. After sputtering of 20 nm Co on either undoped or doped wafers, RTP was done at 487°C for 30 s to form CoSi. A subsequent selective etch and a second RTP step heating the wafer up to 850°C, resulted in a sheet resistance of 3–6Ω/□ on both the active areas and poly-Si gate lines. A “non-bridging” yield, which is in all cases close to 100%, has been found, irrespective of the considered processing parameters.