Details

Autor(en) / Beteiligte

• Chang, C.-W
• Chang, K.-Y
• Chu, Y.-H
• Jou, S.-J

Titel

Near-threshold all-digital PLL with dynamic voltage scaling power management

Ist Teil von

• Electronics letters, 2016-01, Vol.52 (2), p.109-111

Ort / Verlag

The Institution of Engineering and Technology

Erscheinungsjahr

2016

Link zum Volltext

Quelle

Wiley Online Library Journals Frontfile Complete

Beschreibungen/Notizen

• A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V VDD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V VDD, a lock-in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.