Details

Autor(en) / Beteiligte

• Im, Jae-Woo
• Jeong, Woo-Pyo
• Kim, Doo-Hyun
• Nam, Sang-Wan
• Shim, Dong-Kyo
• Choi, Myung-Hoon
• Yoon, Hyun-Jun
• Kim, Dae-Han
• Kim, You-Se
• Park, Hyun-Wook
• Kwak, Dong-Hun
• Park, Sang-Won
• Yoon, Seok-Min
• Hahn, Wook-Ghee
• Ryu, Jin-Ho
• Shim, Sang-Won
• Kang, Kyung-Tae
• Choi, Sung-Ho
• Ihm, Jeong-Don
• Min, Young-Sun
• Kim, In-Mo
• Lee, Doo-Sub
• Cho, Ji-Ho
• Kwon, Oh-Suk
• Lee, Ji-Sang
• Kim, Moo-Sung
• Joo, Sang-Hyun
• Jang, Jae-Hoon
• Hwang, Sang-Won
• Byeon, Dae-Seok
• Yang, Hyang-Ja
• Park, Ki-Tae
• Kyung, Kye-Hyun
• Choi, Jeong-Hyuk

Titel

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Ist Teil von

• 2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

Ort / Verlag

IEEE

Erscheinungsjahr

2015

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].