Details

Autor(en) / Beteiligte

• Koo, Kyung-Hoae
• Wei, Liqiong
• Keane, John
• Bhattacharya, Uddalak
• Karl, Eric A
• Zhang, Kevin

Titel

A 0.094um super(2) high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV V sub(MIN) with read and write assist

Ist Teil von

• 2015 Symposium on VLSI Circuits (VLSI Circuits), 2015-06, p.C266-C267

Erscheinungsjahr

2015

Link zum Volltext

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• A 0.094 mu m super(2) 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write V sub(MIN) assist. A delayed keeper is used for read V sub(MIN) improvement. A 400MHz V sub(MIN) of 560mV is achieved with the proposed design at -10 degree C in volume manufacturing.