Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
A Survey Addressing on High Performance On-Chip VLSI Interconnect
Ist Teil von
International Journal of Electronics and Telecommunications, 2013-09, Vol.59 (3), p.307-312
Ort / Verlag
Warsaw: Polish Academy of Sciences
Erscheinungsjahr
2013
Link zum Volltext
Quelle
EZB Electronic Journals Library
Beschreibungen/Notizen
With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.