Details

Autor(en) / Beteiligte

• Dickson, Timothy O
• Liu, Yong
• Rylov, Sergey V
• Agrawal, Ankur
• Kim, Seongwon
• Hsieh, Ping-Hsuan
• Bulzacchelli, John F
• Ferriss, Mark
• Ainspan, Herschel A
• Rylyakov, Alexander
• Parker, Benjamin D
• Beakes, Michael P
• Baks, Christian
• Shan, Lei
• Kwark, Young
• Tierno, Jose A
• Friedman, Daniel J

Titel

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Ist Teil von

• IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

Erscheinungsjahr

2015

Link zum Volltext

Quelle

IEL

Beschreibungen/Notizen

• A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75" Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20" Megtron-6 PCB traces.