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CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction
Ist Teil von
IEEE transactions on circuits and systems. II, Express briefs, 2009-01, Vol.56 (1), p.11-15
Ort / Verlag
New York: IEEE
Erscheinungsjahr
2009
Quelle
IEEE Electronic Library Online
Beschreibungen/Notizen
A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.