Details

Autor(en) / Beteiligte

• Chao-Chang Chiu
• Po-Hsien Huang
• Lin, Moris
• Ke-Horng Chen
• Ying-Hsi Lin
• Tsung-Yen Tsai
• Chen Chao-Cheng Lee

Titel

A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

Ist Teil von

• IEEE transactions on circuits and systems. I, Regular papers, 2015-01, Vol.62 (1), p.59-69

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2015

Quelle

IEEE

Beschreibungen/Notizen

• The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.