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Indian journal of science and technology, 2013-04, Vol.6 (4), p.4384-4384
Erscheinungsjahr
2013
Link zum Volltext
Quelle
Electronic Journals Library
Beschreibungen/Notizen
It is always being a concern since many years that data moving in networks must be secured from eavesdropping. Data encryption is considered one of the effective methods which challenge cryptanalyst to find the useful information from the encrypted data. Recently this focus has now shifted to encrypting data at rest that is encrypting data for secondary storage devices. The usefulness of this data encryption method is always a challenge for cryptographic researchers to prevent it from cryptanalyst attacks. AES-XTS is the method of encrypting data that is designed for storage devices that provides encryption based on tweak value which makes it less vulnerable for cryptanalyst attacks. This mode has been recently implemented on software as well as hardware. The FPGA provides a way to achieve the fast encryption process with sustainable throughput with a little cost This paper presents an implementation of AES-XTS on FPGA using memory based pipelined design. After successful synthesizing, placement and routing we got the highest efficiency of the proposed design. The implementation is being incorporated by using the Digital Clock Manager (DCM) feature of FPGA with two DCMs are cascaded with the incorporation of on-the-fly key generation to achieve the time effective implementation and also an enhanced implementation of one of the AES sub-modules is incorporated. The proposed scheme is implemented on Virtex V- XC5vlx50-3ff676 FPGA.